English
PULP Platform
Report

PULP Platform

@pulp_platform

A joint effort of @ETH_en, University of Bologna @Unibo + partners for Parallel Ultra-Low Power computing. Boldly designing open hardware since '13.

1.4K Following7.6K Followers3.9K Posts
  1. PULP Platform@pulp_platform
    We introduce "RTSM: Adapting Recursive Models to Multivariate Time-Series Classification" through a learned temporal tokenizer, single-state weight-tied refinement & a pooled sequence-level readout. See our paper
    Download
    0110395
  2. PULP Platform@pulp_platform
    PULP Platform
    RT @LucaBeniniZhFe: We need a strong suite of silicon proven open source designs, and here it is!
    PULP Platform @pulp_platform
    We are delighted to announce the launch of the PULP benchmark suite. It is a collection of practical SystemVerilog designs, with a basic synthesis script with Yosys, a file list, Verilator support & SDC files for ASAP7. Prepared partly for ODE4EC project.
    04028
  3. PULP Platform@pulp_platform
    We are delighted to announce the launch of the PULP benchmark suite. It is a collection of practical SystemVerilog designs, with a basic synthesis script with Yosys, a file list, Verilator support & SDC files for ASAP7. Prepared partly for ODE4EC project.
    Download
    15321.7K
  4. PULP Platform@pulp_platform
    We introduce Spatial-TRM, a compact recursive model with frozen vision-language features, a convex region decoder, and just 11.2M trainable parameters. Check out "Look, Reason, Draw a Region: Recursive Refinement for Spatial Context Prediction"
    Download
    0110523
  5. PULP Platform@pulp_platform
    PULP Platform
    RT @LucaBeniniZhFe: Monte Cimone v3 is a major leap forward in HW and SW maturity and competitiveness for the #RISCV HPC ecosystem! @e4company @Cineca1969
    PULP Platform @pulp_platform
    Assessing the competitiveness of #RISCV against established x86 and Arm processors is difficult. We address this problem in "Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads". See
    02024
  6. PULP Platform@pulp_platform
    Assessing the competitiveness of #RISCV against established x86 and Arm processors is difficult. We address this problem in "Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads". See
    Download
    112794.1K
  7. PULP Platform@pulp_platform
    Check out now Tim's completed doctoral thesis "Scalable Interconnects for Integrated Accelerators" in the ETH Zurich Research Collection. See @fischetim
    Download
    16401.4K
  8. PULP Platform@pulp_platform
    You can now find and download Marco's PhD thesis "Many-Core Programmable Clusters for Open, Software-Defined, and AI-Native Radio Access Networks" in the ETH Zurich Research Collection: @MarcoBertuletti
    Download
    0220825
  9. PULP Platform@pulp_platform
    We are delighted to introduce our new colleague Yuhan! Yuhan will be focusing his research on MAGIA platform integration and deployment for AI models. His research interests include computer architecture and AI accelerator design. Welcome to the team!
    Download
    0021788
  10. PULP Platform@pulp_platform
    We are excited to present Thomy, the first chip we made with an openPDK ICsprout55. Check out &
    Download
    29853.2K
  11. PULP Platform@pulp_platform
    Greetings from #CERN where we have Viviane and Jayanth attending the workshop on Brevitas to dive deep into neural network quantization!
    Download
    0223914
  12. PULP Platform@pulp_platform
    You can now find Yichao's PhD thesis " Toward Thousand-Core Shared Memory: Scalable Many-Core Architectures for Data-Intensive Workloads" in the Research Collection of ETH Zurich: @yichao_zh
    Download
    15331.1K
  13. PULP Platform@pulp_platform
    Cédric, Marc-Andre & Sebastian recently participated at #IUS2026 in Raleigh presenting their work on wearable ultrasound. Check out their papers Have a great weekend!
    Download
    2210885
  14. PULP Platform@pulp_platform
    Kai & Chen recently attended #BEC2026 in Tallinn, meeting with our partners from TalTech & TAICHIP, sharing their research. Kai presented 'PULP4SPACE: Developing Next-Generation Space Processing Platforms' at the TAICHIP special session.
    Download
    0110480
  15. PULP Platform@pulp_platform
    Our new colleague Glenn recently attended #MICCAI2026 in Strasbourg where he presented "S-CEReBrO: Breaking the Memory Barrier in Continuous EEG Monitoring". Check out his paper here:
    Download
    019535
  16. PULP Platform@pulp_platform
    A quick look back at the conference panel "AI as the Chip Designer: Evolution or Illusion?" that took place at #VLSISoC in Cyprus with Frank representing PULP. See for details.
    Download
    01121K
  17. PULP Platform@pulp_platform
    And here is Lorenzo who presented his work "Physically-Aware Preemptive Virtual Channels for Deadlock-Free AXI Networks-on-Chip" at #VLSISoC in Cyprus. Find the poster and slides here:
    Download
    0119751
  18. PULP Platform@pulp_platform
    #VLSISoC is currently underway in Cyprus. Our Bowen is there presenting "Ventaglio: At-the-Roofline Sparse Tensor Contractions on Vector Processors for Transformer Inference". Check out his slides:
    Download
    0119779
  19. PULP Platform@pulp_platform
    Giusy's #IEEESMC2026 slides "A Wearable Multimodal Ultrasound+Inertial System for Real-Time Virtual Reality Interaction" are now online: See also & &
    Download
    01191.1K
  20. PULP Platform@pulp_platform
    Congratulations to Giusy & collaborators who recently won the Best Conference Paper award at IEEE SMC in Seattle for the work "A Wearable Multimodal Ultrasound+Inertial System for Real-Time Virtual Reality Interaction". See the preprint:
    Download
    0013431
  21. Show more posts