#RISC

The $8 Linux computer #Linux #RISC-V @BramStolk @thepine64

Fuck the C series! Rewrote my GPIO wave script in modern C++17 for KianV (RISC-V Linux SoC). Cleaner, faster, and type-safe. #RISC-V #CPlusPlus #FPGA #GPIO #KianV

#RISC-V #Assembly Language #Programming: Unlock the Power of the RISC-V #Instruction Set – Feb. 4 2024 by #Stephen #Smith (Author) @smist08

Before “soft CPU” was a buzzword, Philip and Jan Gray were already doing it. 1991 Philip built the first monolithic soft CPU, 16 bit RISC. 1994/95 @jangray built the first 32 bit RISC. Pioneer era. #fpga #softcore #risc #cpudesign

Oh! 37 new bugs (28 new CVEs) discovered in 5 RISC-V CPUs (e.g., BOOM and CVA6)! #Cascade fuzzes #RISC-V CPUs based on novel basic principles. Try it on your own CPU, it’s open! (with @K_CeesaySeitz @kavehrazavi)

#RISC-V Microprocessor System-On-Chip Design Authors: David #Harris, James #Stine, Sarah Harris, Rose #Thompson

Happy New Year 2025! Hope you all have a marvelous year! Many new projects are coming in 2025 including our new textbook RISC-V Microprocessor System on Chip Design that will be published in Mar 2025 by Elsevier. Grateful to all of you for kindness and support! Go 2025!

Computer Organization and Design The Hardware/Software Interface: #RISC-V Edition David A. #Patterson John L. #Hennessy

#RISC-V KianV #Linux

#RISC-V port of #GLIBC approved.

🔥#China's chip independence plan? #RISC-V might be the answer! As Beijing rumored to drop guidelines for nationwide adoption soon, how will this open-source hot shot shake up #x86 and #Arm's dominance? 💡More: 🔗

$CKB @NervosNetwork continues to scale and become more secure in all the right places at a 🚀rate. They have the foundation to truly enhance user adoption and user experience to all of crypto and blockchains. @joy_protocol #RGB++ #RISC-V #POW $BTC #interoperability

From humanoid robots to #AI servers, Chinese chipmakers are expanding #RISC-V into more demanding computing fields, opening a new chapter for the open architecture in #China's AI industry.

Microchip advances PIC64-HPSC spaceflight computing with key radiation-testing milestones for reliable next-generation spacecraft. #Microchip #SpaceTech #RISC-V #Aerospace @MicrochipTech

Happy Birthday to David Patterson! Patterson received the 2017 #ACMTuringAward for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. #Computing #RISC

▒ Mining Runecoin with RISC MetaProtocol: Innovation on Bitcoin ordinals. ▒ The cryptocurrency world is enriched by #RISC #Metaprotocol, a system that uses the Bitcoin blockchain to introduce a new way to mine and earn $Runecoin Let's find out how it worked and speculate on what it can mine now! ▒ What is RISC MetaProtocol? ▒ RISC (Rune Specific Inscription Circuits) MetaProtocol is a peer-to-peer system that uses Bitcoin ordinals to enable the mining of runes, a fungible token based on Bitcoin. It is designed to leverage the security and decentralization advantages of Bitcoin, while introducing innovative gameplay elements. #Mining #Bitcoin #Ordinals

An Out-of-Order RISC-V processor written in Verilog HDL is now available on #RISC-V #riscv

#laptops + #RISC-V = A #game-changer for #opensource! This #oSC25 session covers upstream work, #openSUSE-specific fixes, packaging, and more.

#ACMTuringAward recipient and #RISC pioneer David Patterson says Moore’s Law is over, and a golden age for computer architecture is about to dawn: “There are Turing Awards waiting to be picked up if people would just work on these things.” @IEEESpectrum

High-performance RISC-V MCUs Meet CH32V407/467 featuring a 200 MHz Qingke V3V core, integrated USB HS PHY, ETH MAC + PHY, up to 8 MB PSRAM, and advanced peripherals for Industrial IoT & Edge AI Fewer components. Faster designs. Smarter systems. #RISC-V

Qwenputer puts a functioning, deterministic RISC-V CPU inside Qwen3.5—a striking example of how far language models can go beyond text generation. #AI #RISC-V #Qwen3.5